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MC10141 Four Bit Universal Shift Register
The MC10141 is a four-bit universal shift register which performs shift left, or shift right, serial/parallel in, and serial/parallel out operations with no external gating. Inputs S1 and S2 control the four possible operations of the register without external gating of the clock. The flip-flops shift information on the positive edge of the clock. The four operations are stop shift, shift left, shift right, and parallel entry of data. The other six inputs are all data type inputs; four for parallel entry data, and one for shifting in from the left (DL) and one for shifting in from the right (DR). * PD = 425 mW typ/pkg (No Load) * fShift = 200 MHz typ * tr, tf = 2.0 ns typ (20%-80%)
LOGIC DIAGRAM
D3 S1 S2 1 of 4 Decode r DR Parallel Enter D2 D1 D0
http://onsemi.com MARKING DIAGRAMS
16 CDIP-16 L SUFFIX CASE 620 1 16 PDIP-16 P SUFFIX CASE 648 1 1 PLCC-20 FN SUFFIX CASE 775 10141 AWLYYWW MC10141P AWLYYWW MC10141L AWLYYWW
Shift Right Shift Left Hold DL
DQ C C
DQ C
DQ C
DQ C
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
DIP PIN ASSIGNMENT
Q0
VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8
Q3
Q2
Q1
VCC1 Q2 Q3 C
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC2 Q1 Q0 DL D0 D1 S1 D2
TRUTH TABLE
SELECT S1 L L H H S2 L H L H OPERATING MODE Parallel Entry Shift Right* Shift Left* Stop Shift Q0n+1 D0 Q1n DL Q0n OUTPUTS Q1n+1 D1 Q2n Q0n Q1n Q2n+1 D2 Q3n Q1n Q2n Q3n+1 D3 DR Q2n Q3n
DR D3 S2 VEE
*Outputs as exist after pulse appears at "C" input with input conditions as shown. (Pulse = Positive transition of clock input).
Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
ORDERING INFORMATION
Device MC10141L MC10141P MC10141FN Package CDIP-16 PDIP-16 PLCC-20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail
(c) Semiconductor Components Industries, LLC, 2002
1
January, 2002 - Rev. 7
Publication Order Number: MC10141/D
MC10141
SHIFT FREQUENCY TEST CIRCUIT
VCC1 = VCC2 +2.0 VDC
VIN
VOUT
COAX
25 uF 1 DL C D0 D1 D2 D3 S1 S2 DR Q3 8 Q2 Q1 16 Q0
0.1 F
Coax
All input and output cables to the scope are equal lengths of 50-ohm coaxial cable. Wire length should be < 1/4 inch from TPin to input pin and TPout to output pin.
INPUT PULSE GENERATOR 50-ohm termination to ground located in each scope channel input.
TEST PROCEDURES: 1. SET D1, D2, D3 = +0.31 VDC (LOGIC L) D0 = +1.11 VDC (LOGIC H) --V IH TO SET Q0 HIGH. 2. APPY CLOCK PULSE VIL 3. MAINTAIN CLOCK LOW. SET S1 = +0.31 VDC (LOGIC L) S2 = +1.11 VDC (LOGIC H) 4. TEST SHIFT FREQUENCY 0.1 F
VEE = -3.2VDC
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MC10141
ELECTRICAL CHARACTERISTICS
Test Limits Pin Under Test 8 5 6 7 4 12 3 3 3 3 3 3 3 3 3 3 0.5 -1.060 -1.890 -1.080 -1.080 -1.080 -1.080 -1.655 -1.655 -1.655 -1.655 -0.890 -1.675 -30C Min Max 112 350 350 390 425 0.5 -0.960 -1.850 -0.980 -0.980 -0.980 -0.980 -1.630 -1.630 -1.630 -1.630 -0.810 -1.650 Min +25C Typ 82 Max 102 220 220 245 265 0.3 -0.890 -1.825 -0.910 -0.910 -0.910 -0.910 -1.595 -1.595 -1.595 -1.595 -0.700 -1.615 Min +85C Max 112 220 220 245 265 Unit mAdc Adc
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH
IinL Output Voltage Output Voltage Logic 1 Logic 0 VOH VOL VOHA (Note 1.)
Adc Vdc Vdc Vdc
Threshold Voltage Logic 1
Threshold Voltage Logic 0
VOLA (Note 1.)
Vdc
Switching Times Load) Propagation Delay Setup TIme (tsetup) Hold Time (thold) Rise Time Fall Time
(50 t4+3+ t12+4+ t10+4+ t4+12+ t3+ t3- fshift 3 14 14 14 3 3 1.7 2.5 5.5 1.5 1.0 1.0 150 P1 VIH VIL 3.9 1.8 2.5 5.0 1.5 1.1 1.1 150 P2 2.9 3.8 2.0 2.5 5.5 1.5 1.1 1.1 150 VIHA VIL P3 VILA VIL 4.2
ns
(20 to 80%) (20 to 80%)
3.4 3.4
2.0 2.0 200
3.3 3.3
3.6 3.6 MHz
Shift Frequency
1. These tests to be performed in sequence as shown. 2. See shift frequency test circuit for test procedures. 3. Reset to zero before performing test. 4. Reset to one before performing test.
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MC10141
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts) @ Test Temperature -30C +25C +85C Pin Under Test 8 5 6 7 4 12 3 3 3 3 3 3 3 3 3 3 6 6 6 Note 3. Note 3. 7 5 6 7 4 4,5,6,7,9, 10,11,13 6 12 VIHmax -0.890 -0.810 -0.700 VILmin -1.890 -1.850 -1.825 VIHAmin -1.205 -1.105 -1.035 VILAmax -1.500 -1.475 -1.440 VEE -5.2 -5.2 -5.2 (VCC) Gnd 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 4 4 4 4 4 4 4 4 4 4 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 +2.0 V 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 P3 VILA VIL
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 -3.2 V P1 P2 P3
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH
IinL Output Voltage Output Voltage Threshold Voltage Logic 1 Logic 0 Logic 1 VOH VOL VOHA (Note 1.)
Threshold Voltage
Logic 0
VOLA (Note 1.)
Note 4. Note 4. 6
6 7
Switching Times (50 Load) Propagation Delay Setup TIme (tsetup) Hold Time (thold) Rise Time Fall Time Shift Frequency (20 to 80%) (20 to 80%) t4+3+ t12+4+ t10+4+ t4+12+ t3+ t3- fshift 3 14 14 14 3 3 Note 2. P1 VIH VIL P2
8 8 8 8 8 8 8 VIHA VIL
1. These tests to be performed in sequence as shown. 2. See shift frequency test circuit for test procedures. 3. Reset to zero before performing test. 4. Reset to one before performing test.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
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MC10141
PACKAGE DIMENSIONS
PLCC-20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C
B -N- Y BRK D -L- -M- W D X V A Z R 0.007 (0.180) 0.007 (0.180)
M
0.007 (0.180) U
M
T L-M
M
S
N
S S
0.007 (0.180)
T L-M
N
S
Z
20
1
G1
0.010 (0.250)
S
T L-M
S
N
S
VIEW D-D T L-M T L-M
S
N N
S
H
0.007 (0.180)
M
T L-M
S
N
S
M
S
S
K1 K
C
E 0.004 (0.100) G G1 0.010 (0.250) S T L-M J -T-
SEATING PLANE
F VIEW S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
0.007 (0.180)
M
T L-M
S
N
S
VIEW S
S
N
S
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2_ 10 _ 0.310 0.330 0.040 ---
MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2_ 10 _ 7.88 8.38 1.02 ---
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MC10141
PACKAGE DIMENSIONS
CDIP-16 L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE T
-A-
16 9
-B-
1 8
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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MC10141
Notes
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MC10141
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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MC10141/D

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